The present invention relates to a semiconductor integrated circuit and, more particularly, to a semiconductor integrated circuit having a double balanced mixer composed of four field effect transistors (hereinafter referred to as "FETs").
A circuit having a double balanced mixer is used to prevent distorsion of electric signals. As shown in FIG. 2, a double balanced mixer section of such a circuit is composed of four FETs 31 to 34 which are symmetrically connected to one another. Respective source electrodes 31a and 32a of the first FET 31 and the second FET 32 form a pair which is connected to a first source terminal S.sub.1. Similarly, respective source electrodes 33a and 34a of a third FET 33 and the fourth FET 34 form a pair which is connected to a second source terminal S.sub.2. On the other side, respective drain electrodes 31b and 33b of the first FET 31 and third FET 33 form a pair which is connected to a first drain terminal D.sub.1. Similarly, respective drain electrodes 32b and 34b of the second FET 32 and fourth FET 34 form a pair which is connected to a second drain terminal D.sub.2. Further, respective gate electrodes 31c and 34c of the first FET 31 and fourth FET 34 form a pair which is connected to a first gate terminal G.sub.1 in order to control voltage applied to each of the FETs. Similarly, respective gate electrodes 32c and 33c of the second FET 32 and third FET 33 form a pair which is connected to a second gate terminal G.sub.2.
FIG. 3 is a plan view showing an example of an conventional electrical wiring for the double balanced mixer of FIG. 2 which is formed on a semiconductor substrate. In this example, the FETs 31 to 34 are arranged so that their gate electrodes 31c to 34c are disposed parallel to one another. Around the FETs 31 to 34, there are provided bonding terminals S.sub.1, S.sub.2, D.sub.1, D.sub.2, G.sub.1 and G.sub.2 as external terminals which are connected to the source electrodes, drain electrodes and gate electrodes of the FETs through interconnection lines 35, respectively.
With such double balanced mixer, it is preferable to make the gate width of each FET larger because gain or noise figure (hereinafter referred to as "NF") of the mixer can be improved thereby. However, if the gate width is made large, the width of each FET would become large with the result that the interconnection line 35 connecting each FET with the corresponding bonding terminal is lengthened. In addition, some of the interconnection lines 35 would need to go around other FETs. This results in a difference in length between the interconnection lines 35. These would affect FET characteristics such as constant K to be described later because an enlarged gate width causes the source/drain resistance to decrease to a value which is substantially the same as that of the resistance of the interconnection line 35.
Further, in a portion A where the interconnection lines 35 intersect, in general the lower interconnection line is formed of a first layer line such as of titanium or aluminum provided on the surface of a semiconductor substrate, while the upper interconnection line is formed of a second layer line such as of aluminum or gold provided on an insulating film intermediate between the first and second layer lines. The sheet resistance of the first layer line per 1 cm.sup.2 is about 100 m.OMEGA., which is about 2.5 times larger than that of the second layer line, or about 40 m.OMEGA.. Accordingly, there is a great difference in resistance between an interconnection line having a first layer line and that not having the same. This results in non-uniformity in operational behavior among the four FETs. Specifically, the relation between a drain current I.sub.d of a FET and a gate voltage V.sub.g thereof is represented by the following equation: EQU Id=K(V.sub.g -V.sub.th).sup.2 (1-.lambda.V.sub.ds)tanh .alpha.V.sub.ds( 1)
where K is a constant in mA/V.sup.2, Vth is a threshold voltage, .lambda. is a channel length modulation, V.sub.ds is a voltage between source and drain, and .alpha. is a tanh constant.
The constant K is greatly affected by the source resistance R.sub.s or gate width W.sub.g of the FET. FIG. 4 shows the relation between the source resistance R.sub.s and a relative value of the constant K, with the gate width W.sub.g as a parameter assuming 100 .mu.m, 200 .mu.m, 400 .mu.m, and 800 .mu.m. As is clear from FIG. 4, a relative value of the constant K greatly decreases with the increase of source resistance R.sub.s, and the larger the gate width W.sub.g, the more conspicuously it affects the rate of change in the constant K.
FIG. 5 shows the relation between the gate width W.sub.g and the constant K, with the source resistance R.sub.s as a parameter assuming 0.OMEGA., 0.5.OMEGA., 0.8.OMEGA., 1.0.OMEGA., 1.4.OMEGA., and 1.8.OMEGA.. As is also clear from FIG. 5, if the gate width becomes larger, the constant K greatly varies depending on the source resistance R.sub.s. Accordingly, although it is preferable to make the gate width larger in view of FET characteristics, it is necessary that the four FETs should have substantially the same source resistance R.sub.s in order to realize uniformity in operational behavior among the FETs.
Further, it is known that a wafer has a variation in electric characteristics such as threshold voltage radially from the center thereof due to, for example, variation in the impurity concentration of a semiconductor substrate, and variation in the thickness of a film nitride. In a semiconductor integrated circuit, which is susceptible to this variation, there is a need to narrow the distance between adjacent FETs so as to relax the influence of variation as much as possible. In addition there can be mentioned non-uniform offsets of the gate electrodes of FETs which also account for the above-mentioned non-uniformity in operational behavior among the FETs. Offsets of a plurality of gate electrodes existing on a wafer are inevitably non-uniform even if the gate electrodes are formed by any method. Particularly, with photolithography which is frequently used for formation of a gate electrode, the alignment precision of an apparatus for photolithography is close to the gate width; hence, non-uniformity in offset among the gate electrodes is not negligible.
The present invention has been attained in view of the above-mentioned circumstances. Thus, it is an object of the present invention to provide a semiconductor integrated circuit wherein interconnection lines associated with four FETs forming a double balanced mixer are made to have substantially the same electrical resistance so as to realize uniformity in operational behavior among the FETs.